ARM Ltd.
IOTKit_CM23
2024.06.02
ARM 32-bit v8-M Baseline based device
CM23
r0p0
little
true
3
false
8
32
DEBUG
Debug
DEBUG
0x0
0x0
0x1000
registers
n
CTRL
0xFFC
32
read-write
n
0x0
0x0
DBGEN
Debug enable (must be 1 to debug)
0
1
NIDEN
Non-intrusive debug enable
1
2
SPIDEN
Secure Debug Enable
2
3
SPNIDEN
Secure Non Invasive Debug
3
4
DMA0
DMA 0 (Non-Secure)
DMA
0x0
0x0
0x510
registers
n
DMA0_ERROR
DMA 0 error interrupt
56
DMA0_TC
DMA 0 terminal count interrupt
57
DMA0
DMA 0 combined interrupt
58
C0Configuration
Channel Configuration Registers
0x110
read-write
n
0x0
0x0
C0Control
Channel Control Registers
0x10C
read-write
n
0x0
0x0
C0DestAddr
Channel Destination Address Registers
0x104
read-write
n
0x0
0x0
C0LLI
Channel Linked List Item Register
0x108
read-write
n
0x0
0x0
C0SrcAddr
Channel Source Address Registers
0x100
read-write
n
0x0
0x0
C1Configuration
Channel Configuration Registers
0x130
read-write
n
0x0
0x0
C1Control
Channel Control Registers
0x12C
read-write
n
0x0
0x0
C1DestAddr
Channel Destination Address Registers
0x124
read-write
n
0x0
0x0
C1LLI
Channel Linked List Item Register
0x128
read-write
n
0x0
0x0
C1SrcAddr
Channel Source Address Registers
0x120
read-write
n
0x0
0x0
Configuration
Configuration Register
0x30
read-write
n
0x0
0x0
EnbldChns
Enabled Channel Register
0x1C
read-only
n
0x0
0x0
IntErrClr
Interrupt Error Clear Register
0x10
write-only
n
0x0
0x0
IntErrorStatus
Interrupt Error Status Register
0xC
read-only
n
0x0
0x0
IntStatus
Interrupt Status Register
0x0
read-write
n
0x0
0x0
IntTCClear
Interrupt Terminal Count Clear Register
0x8
write-only
n
0x0
0x0
IntTCStatus
Interrupt Terminal Count Status Register
0x4
read-only
n
0x0
0x0
ITCR
Test Control Register
0x500
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x504
read-write
n
0x0
0x0
ITOP2
Integration Test Output Register 2
0x508
read-write
n
0x0
0x0
ITOP3
Integration Test Output Register 3
0x50C
read-write
n
0x0
0x0
RawIntErrorStatus
Raw Error Interrupt Status Register
0x18
read-only
n
0x0
0x0
RawIntTCStatus
Raw Interrupt Terminal Count Status Register
0x14
read-only
n
0x0
0x0
SoftBReq
Software Burst Request Register
0x20
read-write
n
0x0
0x0
SoftLBReq
Software Last Burst Request Register
0x28
read-write
n
0x0
0x0
SoftLSReq
Software Last Single Request Register
0x2C
read-write
n
0x0
0x0
SoftSReq
Software Single Request Register
0x24
read-write
n
0x0
0x0
Sync
Synchronization Register
0x34
read-write
n
0x0
0x0
DMA0_SECURE
DMA 0 (Secure)
DMA
0x0
0x0
0x510
registers
n
C0Configuration
Channel Configuration Registers
0x110
read-write
n
0x0
0x0
C0Control
Channel Control Registers
0x10C
read-write
n
0x0
0x0
C0DestAddr
Channel Destination Address Registers
0x104
read-write
n
0x0
0x0
C0LLI
Channel Linked List Item Register
0x108
read-write
n
0x0
0x0
C0SrcAddr
Channel Source Address Registers
0x100
read-write
n
0x0
0x0
C1Configuration
Channel Configuration Registers
0x130
read-write
n
0x0
0x0
C1Control
Channel Control Registers
0x12C
read-write
n
0x0
0x0
C1DestAddr
Channel Destination Address Registers
0x124
read-write
n
0x0
0x0
C1LLI
Channel Linked List Item Register
0x128
read-write
n
0x0
0x0
C1SrcAddr
Channel Source Address Registers
0x120
read-write
n
0x0
0x0
Configuration
Configuration Register
0x30
read-write
n
0x0
0x0
EnbldChns
Enabled Channel Register
0x1C
read-only
n
0x0
0x0
IntErrClr
Interrupt Error Clear Register
0x10
write-only
n
0x0
0x0
IntErrorStatus
Interrupt Error Status Register
0xC
read-only
n
0x0
0x0
IntStatus
Interrupt Status Register
0x0
read-write
n
0x0
0x0
IntTCClear
Interrupt Terminal Count Clear Register
0x8
write-only
n
0x0
0x0
IntTCStatus
Interrupt Terminal Count Status Register
0x4
read-only
n
0x0
0x0
ITCR
Test Control Register
0x500
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x504
read-write
n
0x0
0x0
ITOP2
Integration Test Output Register 2
0x508
read-write
n
0x0
0x0
ITOP3
Integration Test Output Register 3
0x50C
read-write
n
0x0
0x0
RawIntErrorStatus
Raw Error Interrupt Status Register
0x18
read-only
n
0x0
0x0
RawIntTCStatus
Raw Interrupt Terminal Count Status Register
0x14
read-only
n
0x0
0x0
SoftBReq
Software Burst Request Register
0x20
read-write
n
0x0
0x0
SoftLBReq
Software Last Burst Request Register
0x28
read-write
n
0x0
0x0
SoftLSReq
Software Last Single Request Register
0x2C
read-write
n
0x0
0x0
SoftSReq
Software Single Request Register
0x24
read-write
n
0x0
0x0
Sync
Synchronization Register
0x34
read-write
n
0x0
0x0
DMA1
DMA 1 (Non-Secure)
DMA
0x0
0x0
0x510
registers
n
DMA1_ERROR
DMA 1 error interrupt
59
DMA1_TC
DMA 1 terminal count interrupt
60
DMA1
DMA 1 combined interrupt
61
C0Configuration
Channel Configuration Registers
0x110
read-write
n
0x0
0x0
C0Control
Channel Control Registers
0x10C
read-write
n
0x0
0x0
C0DestAddr
Channel Destination Address Registers
0x104
read-write
n
0x0
0x0
C0LLI
Channel Linked List Item Register
0x108
read-write
n
0x0
0x0
C0SrcAddr
Channel Source Address Registers
0x100
read-write
n
0x0
0x0
C1Configuration
Channel Configuration Registers
0x130
read-write
n
0x0
0x0
C1Control
Channel Control Registers
0x12C
read-write
n
0x0
0x0
C1DestAddr
Channel Destination Address Registers
0x124
read-write
n
0x0
0x0
C1LLI
Channel Linked List Item Register
0x128
read-write
n
0x0
0x0
C1SrcAddr
Channel Source Address Registers
0x120
read-write
n
0x0
0x0
Configuration
Configuration Register
0x30
read-write
n
0x0
0x0
EnbldChns
Enabled Channel Register
0x1C
read-only
n
0x0
0x0
IntErrClr
Interrupt Error Clear Register
0x10
write-only
n
0x0
0x0
IntErrorStatus
Interrupt Error Status Register
0xC
read-only
n
0x0
0x0
IntStatus
Interrupt Status Register
0x0
read-write
n
0x0
0x0
IntTCClear
Interrupt Terminal Count Clear Register
0x8
write-only
n
0x0
0x0
IntTCStatus
Interrupt Terminal Count Status Register
0x4
read-only
n
0x0
0x0
ITCR
Test Control Register
0x500
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x504
read-write
n
0x0
0x0
ITOP2
Integration Test Output Register 2
0x508
read-write
n
0x0
0x0
ITOP3
Integration Test Output Register 3
0x50C
read-write
n
0x0
0x0
RawIntErrorStatus
Raw Error Interrupt Status Register
0x18
read-only
n
0x0
0x0
RawIntTCStatus
Raw Interrupt Terminal Count Status Register
0x14
read-only
n
0x0
0x0
SoftBReq
Software Burst Request Register
0x20
read-write
n
0x0
0x0
SoftLBReq
Software Last Burst Request Register
0x28
read-write
n
0x0
0x0
SoftLSReq
Software Last Single Request Register
0x2C
read-write
n
0x0
0x0
SoftSReq
Software Single Request Register
0x24
read-write
n
0x0
0x0
Sync
Synchronization Register
0x34
read-write
n
0x0
0x0
DMA1_SECURE
DMA 1 (Secure)
DMA
0x0
0x0
0x510
registers
n
C0Configuration
Channel Configuration Registers
0x110
read-write
n
0x0
0x0
C0Control
Channel Control Registers
0x10C
read-write
n
0x0
0x0
C0DestAddr
Channel Destination Address Registers
0x104
read-write
n
0x0
0x0
C0LLI
Channel Linked List Item Register
0x108
read-write
n
0x0
0x0
C0SrcAddr
Channel Source Address Registers
0x100
read-write
n
0x0
0x0
C1Configuration
Channel Configuration Registers
0x130
read-write
n
0x0
0x0
C1Control
Channel Control Registers
0x12C
read-write
n
0x0
0x0
C1DestAddr
Channel Destination Address Registers
0x124
read-write
n
0x0
0x0
C1LLI
Channel Linked List Item Register
0x128
read-write
n
0x0
0x0
C1SrcAddr
Channel Source Address Registers
0x120
read-write
n
0x0
0x0
Configuration
Configuration Register
0x30
read-write
n
0x0
0x0
EnbldChns
Enabled Channel Register
0x1C
read-only
n
0x0
0x0
IntErrClr
Interrupt Error Clear Register
0x10
write-only
n
0x0
0x0
IntErrorStatus
Interrupt Error Status Register
0xC
read-only
n
0x0
0x0
IntStatus
Interrupt Status Register
0x0
read-write
n
0x0
0x0
IntTCClear
Interrupt Terminal Count Clear Register
0x8
write-only
n
0x0
0x0
IntTCStatus
Interrupt Terminal Count Status Register
0x4
read-only
n
0x0
0x0
ITCR
Test Control Register
0x500
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x504
read-write
n
0x0
0x0
ITOP2
Integration Test Output Register 2
0x508
read-write
n
0x0
0x0
ITOP3
Integration Test Output Register 3
0x50C
read-write
n
0x0
0x0
RawIntErrorStatus
Raw Error Interrupt Status Register
0x18
read-only
n
0x0
0x0
RawIntTCStatus
Raw Interrupt Terminal Count Status Register
0x14
read-only
n
0x0
0x0
SoftBReq
Software Burst Request Register
0x20
read-write
n
0x0
0x0
SoftLBReq
Software Last Burst Request Register
0x28
read-write
n
0x0
0x0
SoftLSReq
Software Last Single Request Register
0x2C
read-write
n
0x0
0x0
SoftSReq
Software Single Request Register
0x24
read-write
n
0x0
0x0
Sync
Synchronization Register
0x34
read-write
n
0x0
0x0
DMA2
DMA 2 (Non-Secure)
DMA
0x0
0x0
0x510
registers
n
DMA2_ERROR
DMA 2 error interrupt
62
DMA2_TC
DMA 2 terminal count interrupt
63
DMA2
DMA 2 combined interrupt
64
C0Configuration
Channel Configuration Registers
0x110
read-write
n
0x0
0x0
C0Control
Channel Control Registers
0x10C
read-write
n
0x0
0x0
C0DestAddr
Channel Destination Address Registers
0x104
read-write
n
0x0
0x0
C0LLI
Channel Linked List Item Register
0x108
read-write
n
0x0
0x0
C0SrcAddr
Channel Source Address Registers
0x100
read-write
n
0x0
0x0
C1Configuration
Channel Configuration Registers
0x130
read-write
n
0x0
0x0
C1Control
Channel Control Registers
0x12C
read-write
n
0x0
0x0
C1DestAddr
Channel Destination Address Registers
0x124
read-write
n
0x0
0x0
C1LLI
Channel Linked List Item Register
0x128
read-write
n
0x0
0x0
C1SrcAddr
Channel Source Address Registers
0x120
read-write
n
0x0
0x0
Configuration
Configuration Register
0x30
read-write
n
0x0
0x0
EnbldChns
Enabled Channel Register
0x1C
read-only
n
0x0
0x0
IntErrClr
Interrupt Error Clear Register
0x10
write-only
n
0x0
0x0
IntErrorStatus
Interrupt Error Status Register
0xC
read-only
n
0x0
0x0
IntStatus
Interrupt Status Register
0x0
read-write
n
0x0
0x0
IntTCClear
Interrupt Terminal Count Clear Register
0x8
write-only
n
0x0
0x0
IntTCStatus
Interrupt Terminal Count Status Register
0x4
read-only
n
0x0
0x0
ITCR
Test Control Register
0x500
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x504
read-write
n
0x0
0x0
ITOP2
Integration Test Output Register 2
0x508
read-write
n
0x0
0x0
ITOP3
Integration Test Output Register 3
0x50C
read-write
n
0x0
0x0
RawIntErrorStatus
Raw Error Interrupt Status Register
0x18
read-only
n
0x0
0x0
RawIntTCStatus
Raw Interrupt Terminal Count Status Register
0x14
read-only
n
0x0
0x0
SoftBReq
Software Burst Request Register
0x20
read-write
n
0x0
0x0
SoftLBReq
Software Last Burst Request Register
0x28
read-write
n
0x0
0x0
SoftLSReq
Software Last Single Request Register
0x2C
read-write
n
0x0
0x0
SoftSReq
Software Single Request Register
0x24
read-write
n
0x0
0x0
Sync
Synchronization Register
0x34
read-write
n
0x0
0x0
DMA2_SECURE
DMA 2 (Secure)
DMA
0x0
0x0
0x510
registers
n
C0Configuration
Channel Configuration Registers
0x110
read-write
n
0x0
0x0
C0Control
Channel Control Registers
0x10C
read-write
n
0x0
0x0
C0DestAddr
Channel Destination Address Registers
0x104
read-write
n
0x0
0x0
C0LLI
Channel Linked List Item Register
0x108
read-write
n
0x0
0x0
C0SrcAddr
Channel Source Address Registers
0x100
read-write
n
0x0
0x0
C1Configuration
Channel Configuration Registers
0x130
read-write
n
0x0
0x0
C1Control
Channel Control Registers
0x12C
read-write
n
0x0
0x0
C1DestAddr
Channel Destination Address Registers
0x124
read-write
n
0x0
0x0
C1LLI
Channel Linked List Item Register
0x128
read-write
n
0x0
0x0
C1SrcAddr
Channel Source Address Registers
0x120
read-write
n
0x0
0x0
Configuration
Configuration Register
0x30
read-write
n
0x0
0x0
EnbldChns
Enabled Channel Register
0x1C
read-only
n
0x0
0x0
IntErrClr
Interrupt Error Clear Register
0x10
write-only
n
0x0
0x0
IntErrorStatus
Interrupt Error Status Register
0xC
read-only
n
0x0
0x0
IntStatus
Interrupt Status Register
0x0
read-write
n
0x0
0x0
IntTCClear
Interrupt Terminal Count Clear Register
0x8
write-only
n
0x0
0x0
IntTCStatus
Interrupt Terminal Count Status Register
0x4
read-only
n
0x0
0x0
ITCR
Test Control Register
0x500
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x504
read-write
n
0x0
0x0
ITOP2
Integration Test Output Register 2
0x508
read-write
n
0x0
0x0
ITOP3
Integration Test Output Register 3
0x50C
read-write
n
0x0
0x0
RawIntErrorStatus
Raw Error Interrupt Status Register
0x18
read-only
n
0x0
0x0
RawIntTCStatus
Raw Interrupt Terminal Count Status Register
0x14
read-only
n
0x0
0x0
SoftBReq
Software Burst Request Register
0x20
read-write
n
0x0
0x0
SoftLBReq
Software Last Burst Request Register
0x28
read-write
n
0x0
0x0
SoftLSReq
Software Last Single Request Register
0x2C
read-write
n
0x0
0x0
SoftSReq
Software Single Request Register
0x24
read-write
n
0x0
0x0
Sync
Synchronization Register
0x34
read-write
n
0x0
0x0
DMA3
DMA 3 (Non-Secure)
DMA
0x0
0x0
0x510
registers
n
DMA3_ERROR
DMA 3 error interrupt
65
DMA3_TC
DMA 3 terminal count interrupt
66
DMA3
DMA 3 combined interrupt
67
C0Configuration
Channel Configuration Registers
0x110
read-write
n
0x0
0x0
C0Control
Channel Control Registers
0x10C
read-write
n
0x0
0x0
C0DestAddr
Channel Destination Address Registers
0x104
read-write
n
0x0
0x0
C0LLI
Channel Linked List Item Register
0x108
read-write
n
0x0
0x0
C0SrcAddr
Channel Source Address Registers
0x100
read-write
n
0x0
0x0
C1Configuration
Channel Configuration Registers
0x130
read-write
n
0x0
0x0
C1Control
Channel Control Registers
0x12C
read-write
n
0x0
0x0
C1DestAddr
Channel Destination Address Registers
0x124
read-write
n
0x0
0x0
C1LLI
Channel Linked List Item Register
0x128
read-write
n
0x0
0x0
C1SrcAddr
Channel Source Address Registers
0x120
read-write
n
0x0
0x0
Configuration
Configuration Register
0x30
read-write
n
0x0
0x0
EnbldChns
Enabled Channel Register
0x1C
read-only
n
0x0
0x0
IntErrClr
Interrupt Error Clear Register
0x10
write-only
n
0x0
0x0
IntErrorStatus
Interrupt Error Status Register
0xC
read-only
n
0x0
0x0
IntStatus
Interrupt Status Register
0x0
read-write
n
0x0
0x0
IntTCClear
Interrupt Terminal Count Clear Register
0x8
write-only
n
0x0
0x0
IntTCStatus
Interrupt Terminal Count Status Register
0x4
read-only
n
0x0
0x0
ITCR
Test Control Register
0x500
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x504
read-write
n
0x0
0x0
ITOP2
Integration Test Output Register 2
0x508
read-write
n
0x0
0x0
ITOP3
Integration Test Output Register 3
0x50C
read-write
n
0x0
0x0
RawIntErrorStatus
Raw Error Interrupt Status Register
0x18
read-only
n
0x0
0x0
RawIntTCStatus
Raw Interrupt Terminal Count Status Register
0x14
read-only
n
0x0
0x0
SoftBReq
Software Burst Request Register
0x20
read-write
n
0x0
0x0
SoftLBReq
Software Last Burst Request Register
0x28
read-write
n
0x0
0x0
SoftLSReq
Software Last Single Request Register
0x2C
read-write
n
0x0
0x0
SoftSReq
Software Single Request Register
0x24
read-write
n
0x0
0x0
Sync
Synchronization Register
0x34
read-write
n
0x0
0x0
DMA3_SECURE
DMA 3 (Secure)
DMA
0x0
0x0
0x510
registers
n
C0Configuration
Channel Configuration Registers
0x110
read-write
n
0x0
0x0
C0Control
Channel Control Registers
0x10C
read-write
n
0x0
0x0
C0DestAddr
Channel Destination Address Registers
0x104
read-write
n
0x0
0x0
C0LLI
Channel Linked List Item Register
0x108
read-write
n
0x0
0x0
C0SrcAddr
Channel Source Address Registers
0x100
read-write
n
0x0
0x0
C1Configuration
Channel Configuration Registers
0x130
read-write
n
0x0
0x0
C1Control
Channel Control Registers
0x12C
read-write
n
0x0
0x0
C1DestAddr
Channel Destination Address Registers
0x124
read-write
n
0x0
0x0
C1LLI
Channel Linked List Item Register
0x128
read-write
n
0x0
0x0
C1SrcAddr
Channel Source Address Registers
0x120
read-write
n
0x0
0x0
Configuration
Configuration Register
0x30
read-write
n
0x0
0x0
EnbldChns
Enabled Channel Register
0x1C
read-only
n
0x0
0x0
IntErrClr
Interrupt Error Clear Register
0x10
write-only
n
0x0
0x0
IntErrorStatus
Interrupt Error Status Register
0xC
read-only
n
0x0
0x0
IntStatus
Interrupt Status Register
0x0
read-write
n
0x0
0x0
IntTCClear
Interrupt Terminal Count Clear Register
0x8
write-only
n
0x0
0x0
IntTCStatus
Interrupt Terminal Count Status Register
0x4
read-only
n
0x0
0x0
ITCR
Test Control Register
0x500
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x504
read-write
n
0x0
0x0
ITOP2
Integration Test Output Register 2
0x508
read-write
n
0x0
0x0
ITOP3
Integration Test Output Register 3
0x50C
read-write
n
0x0
0x0
RawIntErrorStatus
Raw Error Interrupt Status Register
0x18
read-only
n
0x0
0x0
RawIntTCStatus
Raw Interrupt Terminal Count Status Register
0x14
read-only
n
0x0
0x0
SoftBReq
Software Burst Request Register
0x20
read-write
n
0x0
0x0
SoftLBReq
Software Last Burst Request Register
0x28
read-write
n
0x0
0x0
SoftLSReq
Software Last Single Request Register
0x2C
read-write
n
0x0
0x0
SoftSReq
Software Single Request Register
0x24
read-write
n
0x0
0x0
Sync
Synchronization Register
0x34
read-write
n
0x0
0x0
DUALTIMER
Dual Timer
Timer
0x0
0x0
0x3C
registers
n
DUALTIMER
Dual Timer interrupt
5
TIMER1BGLOAD
Timer 1 Background Load Register
0x18
read-write
n
0x0
0x0
TIMER1CONTROL
Timer 1 Control Register
0x8
read-write
n
0x0
0x0
InterruptEnable
Interrupt Enable bit
5
6
Disable
Interrupt is disabled.
0
Enable
Interrupt is enabled.
1
OneShotCount
Selects one-shot or wrapping counter mode.
0
1
Wrapping
Wrapping counter mode
0
OneShot
One-shot counter mode
1
TimerEnable
Timer Enable Enable bit.
7
8
Disable
Timer is disabled.
0
Enable
Timer is enabled.
1
TimerMode
Timer Mode bit
6
7
Free-Running
Free-Running timer mode.
0
Periodic
Periodic timer mode.
1
TimerPre
Timer prescale bits
2
4
divided by 1
clock is divided by 1
0
divided by 16
clock is divided by 16
1
divided by 256
clock is divided by 256
2
TimerSize
Selects 16-bit or 32- bit counter operation.
1
2
16-bit
16-bit counter mode
0
32-bit
32-bit counter mode
1
TIMER1INTCLR
Timer 1 Interrupt Clear Register
0xC
write-only
n
0x0
0x0
oneToClear
INT
interrupt
0
1
TIMER1LOAD
Timer 1 Load Register
0x0
read-write
n
0x0
0x0
TIMER1MIS
Timer 1 Mask Interrupt Status Register
0x14
read-only
n
0x0
0x0
MIS
Masked Timer interrupt
0
1
TIMER1RIS
Timer 1 Raw Interrupt Status Register
0x10
read-only
n
0x0
0x0
RIS
Raw Timer interrupt
0
1
TIMER1VALUE
Timer 1 Value Register
0x4
read-only
n
0x0
0x0
TIMER2BGLOAD
Timer 2 Background Load Register
0x38
read-write
n
0x0
0x0
TIMER2CONTROL
Timer 2 Control Register
0x28
read-write
n
0x0
0x0
InterruptEnable
Interrupt Enable bit.
5
6
Disable
Interrupt is disabled.
0
Enable
Interrupt is enabled.
1
OneShotCount
Selects one-shot or wrapping counter mode.
0
1
Wrapping
Wrapping counter mode
0
OneShot
One-shot counter mode
1
TimerEnable
Timer Enable Enable bit.
7
1
Disable
Timer is disabled.
0
Enable
Timer is enabled.
1
TimerMode
Timer Mode bit.
6
7
Free-Running
Free-Running timer mode.
0
Periodic
Periodic timer mode.
1
TimerPre
Timer prescale bits.
2
4
divided by 1
clock is divided by 1
0
divided by 16
clock is divided by 16
1
divided by 256
clock is divided by 256
2
TimerSize
Selects 16-bit or 32- bit counter operation.
1
2
16-bit
16-bit counter mode
0
32-bit
32-bit counter mode
1
TIMER2INTCLR
Timer 2 Interrupt Clear Register
0x2C
write-only
n
0x0
0x0
oneToClear
INT
interrupt
0
1
oneToClear
TIMER2LOAD
Timer 2 Load Register
0x20
read-write
n
0x0
0x0
TIMER2MIS
Timer 2 Mask Interrupt Status Register
0x34
read-only
n
0x0
0x0
MIS
Masked Timer interrupt
0
1
TIMER2RIS
Timer 2 Raw Interrupt Status Register
0x30
read-only
n
0x0
0x0
RIS
Raw Timer interrupt
0
1
TIMER2VALUE
Timer 2 Value Register
0x24
read-only
n
0x0
0x0
DUALTIMER_Secure
Dual Timer (Secure)
Timer
0x0
0x0
0x3C
registers
n
TIMER1BGLOAD
Timer 1 Background Load Register
0x18
read-write
n
0x0
0x0
TIMER1CONTROL
Timer 1 Control Register
0x8
read-write
n
0x0
0x0
InterruptEnable
Interrupt Enable bit
5
6
Disable
Interrupt is disabled.
0
Enable
Interrupt is enabled.
1
OneShotCount
Selects one-shot or wrapping counter mode.
0
1
Wrapping
Wrapping counter mode
0
OneShot
One-shot counter mode
1
TimerEnable
Timer Enable Enable bit.
7
8
Disable
Timer is disabled.
0
Enable
Timer is enabled.
1
TimerMode
Timer Mode bit
6
7
Free-Running
Free-Running timer mode.
0
Periodic
Periodic timer mode.
1
TimerPre
Timer prescale bits
2
4
divided by 1
clock is divided by 1
0
divided by 16
clock is divided by 16
1
divided by 256
clock is divided by 256
2
TimerSize
Selects 16-bit or 32- bit counter operation.
1
2
16-bit
16-bit counter mode
0
32-bit
32-bit counter mode
1
TIMER1INTCLR
Timer 1 Interrupt Clear Register
0xC
write-only
n
0x0
0x0
oneToClear
INT
interrupt
0
1
TIMER1LOAD
Timer 1 Load Register
0x0
read-write
n
0x0
0x0
TIMER1MIS
Timer 1 Mask Interrupt Status Register
0x14
read-only
n
0x0
0x0
MIS
Masked Timer interrupt
0
1
TIMER1RIS
Timer 1 Raw Interrupt Status Register
0x10
read-only
n
0x0
0x0
RIS
Raw Timer interrupt
0
1
TIMER1VALUE
Timer 1 Value Register
0x4
read-only
n
0x0
0x0
TIMER2BGLOAD
Timer 2 Background Load Register
0x38
read-write
n
0x0
0x0
TIMER2CONTROL
Timer 2 Control Register
0x28
read-write
n
0x0
0x0
InterruptEnable
Interrupt Enable bit.
5
6
Disable
Interrupt is disabled.
0
Enable
Interrupt is enabled.
1
OneShotCount
Selects one-shot or wrapping counter mode.
0
1
Wrapping
Wrapping counter mode
0
OneShot
One-shot counter mode
1
TimerEnable
Timer Enable Enable bit.
7
1
Disable
Timer is disabled.
0
Enable
Timer is enabled.
1
TimerMode
Timer Mode bit.
6
7
Free-Running
Free-Running timer mode.
0
Periodic
Periodic timer mode.
1
TimerPre
Timer prescale bits.
2
4
divided by 1
clock is divided by 1
0
divided by 16
clock is divided by 16
1
divided by 256
clock is divided by 256
2
TimerSize
Selects 16-bit or 32- bit counter operation.
1
2
16-bit
16-bit counter mode
0
32-bit
32-bit counter mode
1
TIMER2INTCLR
Timer 2 Interrupt Clear Register
0x2C
write-only
n
0x0
0x0
oneToClear
INT
interrupt
0
1
oneToClear
TIMER2LOAD
Timer 2 Load Register
0x20
read-write
n
0x0
0x0
TIMER2MIS
Timer 2 Mask Interrupt Status Register
0x34
read-only
n
0x0
0x0
MIS
Masked Timer interrupt
0
1
TIMER2RIS
Timer 2 Raw Interrupt Status Register
0x30
read-only
n
0x0
0x0
RIS
Raw Timer interrupt
0
1
TIMER2VALUE
Timer 2 Value Register
0x24
read-only
n
0x0
0x0
FPGASYS
FPGA System Control I/O
FPGASYS
0x0
0x0
0x50
registers
n
BUTTON
Button Connections
0x8
read-write
n
0x0
0x0
BUTTON0
0
1
Off
BUTTON is off
0
On
BUTTON is on
1
BUTTON1
1
2
Off
BUTTON is off
0
On
BUTTON is on
1
CLK100HZ
100Hz Up Counter
0x14
read-only
n
0x0
0x0
CLK1HZ
1Hz Up Counter
0x10
read-only
n
0x0
0x0
COUNTER
Cycle up counter
0x18
read-write
n
0x0
0x0
LED
LED Connections
0x0
read-write
n
0x0
0x0
LED0
0
1
Off
LED is off
0
On
LED is on
1
LED1
1
2
Off
LED is off
0
On
LED is on
1
MISC
Misc. Control
0x4C
read-write
n
0x0
0x0
ADC_SPI_nCS
7
8
CLCD_BL_CTRL
6
7
CLCD_CS
0
1
CLCD_RD
5
6
CLCD_RESET
3
4
CLCD_RS
4
5
SHIELD0_SPI_nCS
8
9
SHIELD1_SPI_nCS
9
10
SPI_nSS
1
2
PRESCALER
Reload value for prescaler counter
0x1C
read-write
n
0x0
0x0
PSCNTR
Prescale Counter
0x20
read-write
n
0x0
0x0
FPGASYS_Secure
FPGA System Control I/O (Secure)
FPGASYS
0x0
0x0
0x50
registers
n
BUTTON
Button Connections
0x8
read-write
n
0x0
0x0
BUTTON0
0
1
Off
BUTTON is off
0
On
BUTTON is on
1
BUTTON1
1
2
Off
BUTTON is off
0
On
BUTTON is on
1
CLK100HZ
100Hz Up Counter
0x14
read-only
n
0x0
0x0
CLK1HZ
1Hz Up Counter
0x10
read-only
n
0x0
0x0
COUNTER
Cycle up counter
0x18
read-write
n
0x0
0x0
LED
LED Connections
0x0
read-write
n
0x0
0x0
LED0
0
1
Off
LED is off
0
On
LED is on
1
LED1
1
2
Off
LED is off
0
On
LED is on
1
MISC
Misc. Control
0x4C
read-write
n
0x0
0x0
ADC_SPI_nCS
7
8
CLCD_BL_CTRL
6
7
CLCD_CS
0
1
CLCD_RD
5
6
CLCD_RESET
3
4
CLCD_RS
4
5
SHIELD0_SPI_nCS
8
9
SHIELD1_SPI_nCS
9
10
SPI_nSS
1
2
PRESCALER
Reload value for prescaler counter
0x1C
read-write
n
0x0
0x0
PSCNTR
Prescale Counter
0x20
read-write
n
0x0
0x0
GPIO0
GPIO 0 (Non-Secure)
GPIO
0x0
0x0
0x3C
registers
n
GPIO0
GPIO 0 combined interrupt
68
GPIO0_0
GPIO 0 Pin 0 interrupt
72
GPIO0_1
GPIO 0 Pin 1 interrupt
73
GPIO0_2
GPIO 0 Pin 2 interrupt
74
GPIO0_3
GPIO 0 Pin 3 interrupt
75
GPIO0_4
GPIO 0 Pin 4 interrupt
76
GPIO0_5
GPIO 0 Pin 5 interrupt
77
GPIO0_6
GPIO 0 Pin 6 interrupt
78
GPIO0_7
GPIO 0 Pin 7 interrupt
79
GPIO0_8
GPIO 0 Pin 8 interrupt
80
GPIO0_9
GPIO 0 Pin 9 interrupt
81
GPIO0_10
GPIO 0 Pin 10 interrupt
82
GPIO0_11
GPIO 0 Pin 11 interrupt
83
GPIO0_12
GPIO 0 Pin 12 interrupt
84
GPIO0_13
GPIO 0 Pin 13 interrupt
85
GPIO0_14
GPIO 0 Pin 14 interrupt
86
GPIO0_15
GPIO 0 Pin 15 interrupt
87
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO0_Secure
GPIO 0 (Secure)
GPIO
0x0
0x0
0x3C
registers
n
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO1
GPIO 1 (Non-Secure)
GPIO
0x0
0x0
0x3C
registers
n
GPIO1
GPIO 1 combined interrupt
69
GPIO1_0
GPIO 1 Pin 0 interrupt
88
GPIO1_1
GPIO 1 Pin 1 interrupt
89
GPIO1_2
GPIO 1 Pin 2 interrupt
90
GPIO1_3
GPIO 1 Pin 3 interrupt
91
GPIO1_4
GPIO 1 Pin 4 interrupt
92
GPIO1_5
GPIO 1 Pin 5 interrupt
93
GPIO1_6
GPIO 1 Pin 6 interrupt
94
GPIO1_7
GPIO 1 Pin 7 interrupt
95
GPIO1_8
GPIO 1 Pin 8 interrupt
96
GPIO1_9
GPIO 1 Pin 9 interrupt
97
GPIO1_10
GPIO 1 Pin 10 interrupt
98
GPIO1_11
GPIO 1 Pin 11 interrupt
99
GPIO1_12
GPIO 1 Pin 12 interrupt
100
GPIO1_13
GPIO 1 Pin 13 interrupt
101
GPIO1_14
GPIO 1 Pin 14 interrupt
102
GPIO1_15
GPIO 1 Pin 15 interrupt
103
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO1_Secure
GPIO 1 (Secure)
GPIO
0x0
0x0
0x3C
registers
n
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO2
GPIO 2 (Non-Secure)
GPIO
0x0
0x0
0x3C
registers
n
GPIO2
GPIO 2 combined interrupt
70
GPIO2_0
GPIO 2 Pin 0 interrupt
104
GPIO2_1
GPIO 2 Pin 1 interrupt
105
GPIO2_2
GPIO 2 Pin 2 interrupt
106
GPIO2_3
GPIO 2 Pin 3 interrupt
107
GPIO2_4
GPIO 2 Pin 4 interrupt
108
GPIO2_5
GPIO 2 Pin 5 interrupt
109
GPIO2_6
GPIO 2 Pin 6 interrupt
110
GPIO2_7
GPIO 2 Pin 7 interrupt
111
GPIO2_8
GPIO 2 Pin 8 interrupt
112
GPIO2_9
GPIO 2 Pin 9 interrupt
113
GPIO2_10
GPIO 2 Pin 10 interrupt
114
GPIO2_11
GPIO 2 Pin 11 interrupt
115
GPIO2_12
GPIO 2 Pin 12 interrupt
116
GPIO2_13
GPIO 2 Pin 13 interrupt
117
GPIO2_14
GPIO 2 Pin 14 interrupt
118
GPIO2_15
GPIO 2 Pin 15 interrupt
119
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO2_Secure
GPIO 2 (Secure)
GPIO
0x0
0x0
0x3C
registers
n
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO3
GPIO 3 (Non-Secure)
GPIO
0x0
0x0
0x3C
registers
n
GPIO3
GPIO 3 combined interrupt
71
GPIO3_0
GPIO 3 Pin 0 interrupt
120
GPIO3_1
GPIO 3 Pin 1 interrupt
121
GPIO3_2
GPIO 3 Pin 2 interrupt
122
GPIO3_3
GPIO 3 Pin 3 interrupt
123
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
GPIO3_Secure
GPIO 3 (Secure)
GPIO
0x0
0x0
0x3C
registers
n
ALTFUNCCLR
Alternate function clear Register
0x1C
read-write
n
0x0
0x0
ALTFUNCSET
Alternate function set Register
0x18
read-write
n
0x0
0x0
DATA
Data Register
0x0
read-write
n
0x0
0x0
DATAOUT
Data Output Register
0x4
read-write
n
0x0
0x0
INTCLEAR
Interrupt CLEAR Register
INTSTATUS
0x38
write-only
n
0x0
0x0
oneToClear
INTENCLR
Interrupt enable clear Register
0x24
read-write
n
0x0
0x0
INTENSET
Interrupt enable set Register
0x20
read-write
n
0x0
0x0
INTPOLCLR
Polarity-level, edge interrupt configuration clear Register
0x34
read-write
n
0x0
0x0
INTPOLSET
Polarity-level, edge interrupt configuration set Register
0x30
read-write
n
0x0
0x0
INTSTATUS
Interrupt Status Register
0x38
read-only
n
0x0
0x0
INTTYPECLR
Interrupt type clear Register
0x2C
read-write
n
0x0
0x0
INTTYPESET
Interrupt type set Register
0x28
read-write
n
0x0
0x0
OUTENCLR
Ouptut enable clear Register
0x14
read-write
n
0x0
0x0
OUTENSET
Ouptut enable set Register
0x10
read-write
n
0x0
0x0
I2C0
I2C 0 (Non-Secure)
I2C
0x0
0x0
0xC
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2C0_Secure
I2C 0 (Secure)
I2C
0x0
0x0
0xC
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2C1
I2C 1 (Non-Secure)
I2C
0x0
0x0
0xC
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2C1_Secure
I2C 1 (Secure)
I2C
0x0
0x0
0xC
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2C2
I2C 2 (Non-Secure)
I2C
0x0
0x0
0xC
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2C2_Secure
I2C 2 (Secure)
I2C
0x0
0x0
0xC
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2C3
I2C 3 (Non-Secure)
I2C
0x0
0x0
0xC
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2C3_Secure
I2C 3 (Secure)
I2C
0x0
0x0
0xC
registers
n
CONTROL
Control Status
0x0
read-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLC
Control Clear
0x4
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
CONTROLS
Control Set
CONTROL
0x0
write-only
n
0x0
0x0
SCL
Serial clock line
0
1
SDA
Serial data line
1
2
I2S
simple audio I2S peripheral (Non-Secure)
I2S
0x0
0x0
0x30C
registers
n
I2S
I2S interrupt
49
CONTROL
CONTROL Register
0x0
read-write
n
0x0
0x0
DIVIDE
Divide ratio Register
0xC
read-write
n
0x0
0x0
ERROR
Error Status Register
0x8
read-write
n
0x0
0x0
ITCR
Integration Test Control Register
0x300
read-write
n
0x0
0x0
ITIP1
Integration Test Input Register 1
0x304
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x308
read-write
n
0x0
0x0
RXBUF
Receive Buffer
0x14
read-only
n
0x0
0x0
STATUS
STATUS Register
0x4
read-only
n
0x0
0x0
TXBUF
Transmit Buffer
0x10
write-only
n
0x0
0x0
I2S_Secure
simple audio I2S peripheral (Secure)
I2S
0x0
0x0
0x30C
registers
n
CONTROL
CONTROL Register
0x0
read-write
n
0x0
0x0
DIVIDE
Divide ratio Register
0xC
read-write
n
0x0
0x0
ERROR
Error Status Register
0x8
read-write
n
0x0
0x0
ITCR
Integration Test Control Register
0x300
read-write
n
0x0
0x0
ITIP1
Integration Test Input Register 1
0x304
read-write
n
0x0
0x0
ITOP1
Integration Test Output Register 1
0x308
read-write
n
0x0
0x0
RXBUF
Receive Buffer
0x14
read-only
n
0x0
0x0
STATUS
STATUS Register
0x4
read-only
n
0x0
0x0
TXBUF
Transmit Buffer
0x10
write-only
n
0x0
0x0
MPC_SSRAM1
Memory Protection Controller SSRAM1
MPC
0x0
0x0
0x38
registers
n
BLK_CFG
Block Configuration Register
0x14
read-only
n
0x0
0x0
BLK_IDX
Block Index Register
0x18
read-write
n
0x0
0x0
BLK_LUT
Block Lookup Tabe Register
0x1C
read-write
n
0x0
0x0
BLK_MAX
Block Maximum Register
0x10
read-only
n
0x0
0x0
CTRL
Control Register
0x0
read-write
n
0x0
0x0
INT_CLEAR
Interrupt Clear Register
0x24
write-only
n
0x0
0x0
INT_EN
Interrupt Enable Register
0x28
read-write
n
0x0
0x0
INT_INFO1
Interrupt Info1 Register
0x2C
read-only
n
0x0
0x0
INT_INFO2
Interrupt Info2 Register
0x30
read-only
n
0x0
0x0
INT_SET
Interrupt Set Register
0x34
write-only
n
0x0
0x0
INT_STAT
Interrupt Status Register
0x20
read-only
n
0x0
0x0
MPC_SSRAM2
Memory Protection Controller SSRAM2
MPC
0x0
0x0
0x38
registers
n
BLK_CFG
Block Configuration Register
0x14
read-only
n
0x0
0x0
BLK_IDX
Block Index Register
0x18
read-write
n
0x0
0x0
BLK_LUT
Block Lookup Tabe Register
0x1C
read-write
n
0x0
0x0
BLK_MAX
Block Maximum Register
0x10
read-only
n
0x0
0x0
CTRL
Control Register
0x0
read-write
n
0x0
0x0
INT_CLEAR
Interrupt Clear Register
0x24
write-only
n
0x0
0x0
INT_EN
Interrupt Enable Register
0x28
read-write
n
0x0
0x0
INT_INFO1
Interrupt Info1 Register
0x2C
read-only
n
0x0
0x0
INT_INFO2
Interrupt Info2 Register
0x30
read-only
n
0x0
0x0
INT_SET
Interrupt Set Register
0x34
write-only
n
0x0
0x0
INT_STAT
Interrupt Status Register
0x20
read-only
n
0x0
0x0
MPC_SSRAM3
Memory Protection Controller SSRAM3
MPC
0x0
0x0
0x38
registers
n
BLK_CFG
Block Configuration Register
0x14
read-only
n
0x0
0x0
BLK_IDX
Block Index Register
0x18
read-write
n
0x0
0x0
BLK_LUT
Block Lookup Tabe Register
0x1C
read-write
n
0x0
0x0
BLK_MAX
Block Maximum Register
0x10
read-only
n
0x0
0x0
CTRL
Control Register
0x0
read-write
n
0x0
0x0
INT_CLEAR
Interrupt Clear Register
0x24
write-only
n
0x0
0x0
INT_EN
Interrupt Enable Register
0x28
read-write
n
0x0
0x0
INT_INFO1
Interrupt Info1 Register
0x2C
read-only
n
0x0
0x0
INT_INFO2
Interrupt Info2 Register
0x30
read-only
n
0x0
0x0
INT_SET
Interrupt Set Register
0x34
write-only
n
0x0
0x0
INT_STAT
Interrupt Status Register
0x20
read-only
n
0x0
0x0
NSPC
Non-Secure Privilege Control Block
NSPC
0x0
0x0
0xD0
registers
n
AHBNSPPPC0
Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x90
-1
read-write
n
0x0
0x0
AHBNSPPPC1
Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x94
-1
read-write
n
0x0
0x0
AHBNSPPPC2
Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x98
-1
read-write
n
0x0
0x0
AHBNSPPPC3
Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x9C
-1
read-write
n
0x0
0x0
AHBNSPPPCEXP0
Expansion 0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0xA0
-1
read-write
n
0x0
0x0
AHBNSPPPCEXP1
Expansion 0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0xA4
-1
read-write
n
0x0
0x0
AHBNSPPPCEXP2
Expansion 0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0xA8
-1
read-write
n
0x0
0x0
AHBNSPPPCEXP3
Expansion 0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0xAC
-1
read-write
n
0x0
0x0
AHBNSPPPCEXP[0]
Expansion 0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x140
read-write
n
0x0
0x0
AHBNSPPPCEXP[1]
Expansion 0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x1E4
read-write
n
0x0
0x0
AHBNSPPPCEXP[2]
Expansion 0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x28C
read-write
n
0x0
0x0
AHBNSPPPCEXP[3]
Expansion 0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x338
read-write
n
0x0
0x0
AHBNSPPPC[0]
Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x120
read-write
n
0x0
0x0
AHBNSPPPC[1]
Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x1B4
read-write
n
0x0
0x0
AHBNSPPPC[2]
Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x24C
read-write
n
0x0
0x0
AHBNSPPPC[3]
Non-Secure Unprivileged Access AHB slave Peripheral Protection Control
0x2E8
read-write
n
0x0
0x0
APBNSPPPC0
Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0xB0
-1
read-write
n
0x0
0x0
APBNSPPPC1
Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0xB4
-1
read-write
n
0x0
0x0
APBNSPPPC2
Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0xB8
-1
read-write
n
0x0
0x0
APBNSPPPC3
Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0xBC
-1
read-write
n
0x0
0x0
APBNSPPPCEXP0
Expansion 0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0xC0
-1
read-write
n
0x0
0x0
APBNSPPPCEXP1
Expansion 0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0xC4
-1
read-write
n
0x0
0x0
APBNSPPPCEXP2
Expansion 0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0xC8
-1
read-write
n
0x0
0x0
APBNSPPPCEXP3
Expansion 0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0xCC
-1
read-write
n
0x0
0x0
APBNSPPPCEXP[0]
Expansion 0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0x180
read-write
n
0x0
0x0
APBNSPPPCEXP[1]
Expansion 0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0x244
read-write
n
0x0
0x0
APBNSPPPCEXP[2]
Expansion 0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0x30C
read-write
n
0x0
0x0
APBNSPPPCEXP[3]
Expansion 0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0x3D8
read-write
n
0x0
0x0
APBNSPPPC[0]
Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0x160
read-write
n
0x0
0x0
APBNSPPPC[1]
Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0x214
read-write
n
0x0
0x0
APBNSPPPC[2]
Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0x2CC
read-write
n
0x0
0x0
APBNSPPPC[3]
Non-Secure Unprivileged Access APB slave Peripheral Protection Control
0x388
read-write
n
0x0
0x0
SCC
Serial Communication Controller
SCC
0x0
0x0
0x1000
registers
n
AID
AID register
0xFF8
read-only
n
0x0
0x0
FPGA_BUILD
FPGA Build Number
24
32
MPS2_REV
V2M-MPS2 target Board Revision
20
24
A
Revision A
0
B
Revision B
1
C
Revision C
2
NUM_CFG_REG
Number of SCC configuration register
0
8
CFG_REG0
Configuration register 0
0x0
read-write
n
0x0
0x0
REMAP
REMAP Block RAM to ZBT
0
1
CFG_REG1
Configuration register 1
0x4
read-write
n
0x0
0x0
MCC_LED0
MCC LED 0
0
1
Off
LED is off
0
On
LED is on
1
MCC_LED1
MCC LED 1
1
2
Off
LED is off
0
On
LED is on
1
MCC_LED2
MCC LED 2
2
3
Off
LED is off
0
On
LED is on
1
MCC_LED3
MCC LED 3
3
4
Off
LED is off
0
On
LED is on
1
MCC_LED4
MCC LED 4
4
5
Off
LED is off
0
On
LED is on
1
MCC_LED5
MCC LED 5
5
6
Off
LED is off
0
On
LED is on
1
MCC_LED6
MCC LED 6
6
7
Off
LED is off
0
On
LED is on
1
MCC_LED7
MCC LED 7
7
8
Off
LED is off
0
On
LED is on
1
CFG_REG2
Configuration register 2
0x8
read-only
n
0x0
0x0
CFG_REG3
Configuration register 3
0xC
read-only
n
0x0
0x0
MCC_SWITCH1
MCC switch 1
1
2
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH2
MCC switch 2
2
3
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH3
MCC switch 3
3
4
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH4
MCC switch 4
4
5
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH5
MCC switch 5
5
6
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH6
MCC switch 6
6
7
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH7
MCC switch 7
7
8
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCHE0
MCC switch 0
0
1
Off
Switch is off
0
On
Switch is on
1
CFG_REG4
Configuration register 4
0x10
read-only
n
0x0
0x0
BRDREV
Board Revision
0
4
CFG_REG5
0x14
read-write
n
0x0
0x0
DEBUG
Debug connection
5
6
SWD
Serial Wire Debug
0
JTAG
JTAG
1
CFG_REG6
0x18
read-only
n
0x0
0x0
CFG_REG7
0x1C
read-only
n
0x0
0x0
DLL
DLL Lock Register
0x100
read-write
n
0x0
0x0
LOCKED
Complete Flag
0
1
LOCKED_MASKED
Error Flag
24
32
LOCK_UNLOCK
Complete Flag
16
24
ID
AID register
0xFFC
read-only
n
0x0
0x0
APP_NOTE_VAR
Application note IP variant number
20
24
APP_REV
Application note IP revision number
0
4
IMPLEMENTER_ID
Implementer ID: 0x41 = ARM
24
32
ARM
ARM
0x41
IP_ARCH
IP Architecture
16
20
AHB
AHB
0x4
PRI_NUM
Primary Part Number: 383 = AN383
4
12
SYS_CFGCTRL
System configuration control register
0xA8
read-write
n
0x0
0x0
DEVICE
Device (value of 0/1/2 for supported clocks
0
12
RFUNCVAL
Function value
20
26
RW_ACCESS
Read/Write Access
30
31
START
Start: generates interrupt on write to this bit
31
32
SYS_CFGDATA_OUT
System configuration data register OUT
0xA4
read-write
n
0x0
0x0
SYS_CFGDATA_RTN
System configuration data register RTN
0xA0
read-write
n
0x0
0x0
SYS_CFGSTAT
System configuration status register
0xAC
read-write
n
0x0
0x0
COMPLETE
Complete Flag
0
1
ERROR
Error Flag
1
2
SCC_Secure
Serial Communication Controller I/O (Secure)
SCC
0x0
0x0
0x1000
registers
n
AID
AID register
0xFF8
read-only
n
0x0
0x0
FPGA_BUILD
FPGA Build Number
24
32
MPS2_REV
V2M-MPS2 target Board Revision
20
24
A
Revision A
0
B
Revision B
1
C
Revision C
2
NUM_CFG_REG
Number of SCC configuration register
0
8
CFG_REG0
Configuration register 0
0x0
read-write
n
0x0
0x0
REMAP
REMAP Block RAM to ZBT
0
1
CFG_REG1
Configuration register 1
0x4
read-write
n
0x0
0x0
MCC_LED0
MCC LED 0
0
1
Off
LED is off
0
On
LED is on
1
MCC_LED1
MCC LED 1
1
2
Off
LED is off
0
On
LED is on
1
MCC_LED2
MCC LED 2
2
3
Off
LED is off
0
On
LED is on
1
MCC_LED3
MCC LED 3
3
4
Off
LED is off
0
On
LED is on
1
MCC_LED4
MCC LED 4
4
5
Off
LED is off
0
On
LED is on
1
MCC_LED5
MCC LED 5
5
6
Off
LED is off
0
On
LED is on
1
MCC_LED6
MCC LED 6
6
7
Off
LED is off
0
On
LED is on
1
MCC_LED7
MCC LED 7
7
8
Off
LED is off
0
On
LED is on
1
CFG_REG2
Configuration register 2
0x8
read-only
n
0x0
0x0
CFG_REG3
Configuration register 3
0xC
read-only
n
0x0
0x0
MCC_SWITCH1
MCC switch 1
1
2
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH2
MCC switch 2
2
3
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH3
MCC switch 3
3
4
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH4
MCC switch 4
4
5
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH5
MCC switch 5
5
6
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH6
MCC switch 6
6
7
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCH7
MCC switch 7
7
8
Off
Switch is off
0
On
Switch is on
1
MCC_SWITCHE0
MCC switch 0
0
1
Off
Switch is off
0
On
Switch is on
1
CFG_REG4
Configuration register 4
0x10
read-only
n
0x0
0x0
BRDREV
Board Revision
0
4
CFG_REG5
0x14
read-write
n
0x0
0x0
DEBUG
Debug connection
5
6
SWD
Serial Wire Debug
0
JTAG
JTAG
1
CFG_REG6
0x18
read-only
n
0x0
0x0
CFG_REG7
0x1C
read-only
n
0x0
0x0
DLL
DLL Lock Register
0x100
read-write
n
0x0
0x0
LOCKED
Complete Flag
0
1
LOCKED_MASKED
Error Flag
24
32
LOCK_UNLOCK
Complete Flag
16
24
ID
AID register
0xFFC
read-only
n
0x0
0x0
APP_NOTE_VAR
Application note IP variant number
20
24
APP_REV
Application note IP revision number
0
4
IMPLEMENTER_ID
Implementer ID: 0x41 = ARM
24
32
ARM
ARM
0x41
IP_ARCH
IP Architecture
16
20
AHB
AHB
0x4
PRI_NUM
Primary Part Number: 383 = AN383
4
12
SYS_CFGCTRL
System configuration control register
0xA8
read-write
n
0x0
0x0
DEVICE
Device (value of 0/1/2 for supported clocks
0
12
RFUNCVAL
Function value
20
26
RW_ACCESS
Read/Write Access
30
31
START
Start: generates interrupt on write to this bit
31
32
SYS_CFGDATA_OUT
System configuration data register OUT
0xA4
read-write
n
0x0
0x0
SYS_CFGDATA_RTN
System configuration data register RTN
0xA0
read-write
n
0x0
0x0
SYS_CFGSTAT
System configuration status register
0xAC
read-write
n
0x0
0x0
COMPLETE
Complete Flag
0
1
ERROR
Error Flag
1
2
SPC
Secure Privilege Control Block
SPC
0x0
0x0
0xD4
registers
n
AHBNSPPC0
Non-Secure Access AHB slave Peripheral Protection Control
0x50
-1
read-write
n
0x0
0x0
AHBNSPPC1
Non-Secure Access AHB slave Peripheral Protection Control
0x54
-1
read-write
n
0x0
0x0
AHBNSPPC2
Non-Secure Access AHB slave Peripheral Protection Control
0x58
-1
read-write
n
0x0
0x0
AHBNSPPC3
Non-Secure Access AHB slave Peripheral Protection Control
0x5C
-1
read-write
n
0x0
0x0
AHBNSPPCEXP0
Expansion Non_Secure Access AHB slave Peripheral Protection Control
0x60
-1
read-write
n
0x0
0x0
AHBNSPPCEXP1
Expansion Non_Secure Access AHB slave Peripheral Protection Control
0x64
-1
read-write
n
0x0
0x0
AHBNSPPCEXP2
Expansion Non_Secure Access AHB slave Peripheral Protection Control
0x68
-1
read-write
n
0x0
0x0
AHBNSPPCEXP3
Expansion Non_Secure Access AHB slave Peripheral Protection Control
0x6C
-1
read-write
n
0x0
0x0
AHBNSPPCEXP[0]
Expansion Non_Secure Access AHB slave Peripheral Protection Control
0xC0
read-write
n
0x0
0x0
AHBNSPPCEXP[1]
Expansion Non_Secure Access AHB slave Peripheral Protection Control
0x124
read-write
n
0x0
0x0
AHBNSPPCEXP[2]
Expansion Non_Secure Access AHB slave Peripheral Protection Control
0x18C
read-write
n
0x0
0x0
AHBNSPPCEXP[3]
Expansion Non_Secure Access AHB slave Peripheral Protection Control
0x1F8
read-write
n
0x0
0x0
AHBNSPPC[0]
Non-Secure Access AHB slave Peripheral Protection Control
0xA0
read-write
n
0x0
0x0
AHBNSPPC[1]
Non-Secure Access AHB slave Peripheral Protection Control
0xF4
read-write
n
0x0
0x0
AHBNSPPC[2]
Non-Secure Access AHB slave Peripheral Protection Control
0x14C
read-write
n
0x0
0x0
AHBNSPPC[3]
Non-Secure Access AHB slave Peripheral Protection Control
0x1A8
read-write
n
0x0
0x0
AHBSPPPC0
Secure Unprivileged Access AHB slave Peripheral Protection Control
0x90
-1
read-only
n
0x0
0x0
AHBSPPPC1
Secure Unprivileged Access AHB slave Peripheral Protection Control
0x94
-1
read-only
n
0x0
0x0
AHBSPPPC2
Secure Unprivileged Access AHB slave Peripheral Protection Control
0x98
-1
read-only
n
0x0
0x0
AHBSPPPC3
Secure Unprivileged Access AHB slave Peripheral Protection Control
0x9C
-1
read-only
n
0x0
0x0
AHBSPPPCEXP0
Expansion Secure Unprivileged Access AHB slave Peripheral Protection Control
0xA0
-1
read-write
n
0x0
0x0
AHBSPPPCEXP1
Expansion Secure Unprivileged Access AHB slave Peripheral Protection Control
0xA4
-1
read-write
n
0x0
0x0
AHBSPPPCEXP2
Expansion Secure Unprivileged Access AHB slave Peripheral Protection Control
0xA8
-1
read-write
n
0x0
0x0
AHBSPPPCEXP3
Expansion Secure Unprivileged Access AHB slave Peripheral Protection Control
0xAC
-1
read-write
n
0x0
0x0
AHBSPPPCEXP[0]
Expansion Secure Unprivileged Access AHB slave Peripheral Protection Control
0x140
read-write
n
0x0
0x0
AHBSPPPCEXP[1]
Expansion Secure Unprivileged Access AHB slave Peripheral Protection Control
0x1E4
read-write
n
0x0
0x0
AHBSPPPCEXP[2]
Expansion Secure Unprivileged Access AHB slave Peripheral Protection Control
0x28C
read-write
n
0x0
0x0
AHBSPPPCEXP[3]
Expansion Secure Unprivileged Access AHB slave Peripheral Protection Control
0x338
read-write
n
0x0
0x0
AHBSPPPC[0]
Secure Unprivileged Access AHB slave Peripheral Protection Control
0x120
read-only
n
0x0
0x0
AHBSPPPC[1]
Secure Unprivileged Access AHB slave Peripheral Protection Control
0x1B4
read-only
n
0x0
0x0
AHBSPPPC[2]
Secure Unprivileged Access AHB slave Peripheral Protection Control
0x24C
read-only
n
0x0
0x0
AHBSPPPC[3]
Secure Unprivileged Access AHB slave Peripheral Protection Control
0x2E8
read-only
n
0x0
0x0
APBNSPPC0
Non-Secure Access APB slave Peripheral Protection Control
0x70
-1
read-write
n
0x0
0x0
APBNSPPC1
Non-Secure Access APB slave Peripheral Protection Control
0x74
-1
read-write
n
0x0
0x0
APBNSPPC2
Non-Secure Access APB slave Peripheral Protection Control
0x78
-1
read-write
n
0x0
0x0
APBNSPPC3
Non-Secure Access APB slave Peripheral Protection Control
0x7C
-1
read-write
n
0x0
0x0
APBNSPPCEXP0
Expansion Non_Secure Access APB slave Peripheral Protection Control
0x80
-1
read-write
n
0x0
0x0
APBNSPPCEXP1
Expansion Non_Secure Access APB slave Peripheral Protection Control
0x84
-1
read-write
n
0x0
0x0
APBNSPPCEXP2
Expansion Non_Secure Access APB slave Peripheral Protection Control
0x88
-1
read-write
n
0x0
0x0
APBNSPPCEXP3
Expansion Non_Secure Access APB slave Peripheral Protection Control
0x8C
-1
read-write
n
0x0
0x0
APBNSPPCEXP[0]
Expansion Non_Secure Access APB slave Peripheral Protection Control
0x100
read-write
n
0x0
0x0
APBNSPPCEXP[1]
Expansion Non_Secure Access APB slave Peripheral Protection Control
0x184
read-write
n
0x0
0x0
APBNSPPCEXP[2]
Expansion Non_Secure Access APB slave Peripheral Protection Control
0x20C
read-write
n
0x0
0x0
APBNSPPCEXP[3]
Expansion Non_Secure Access APB slave Peripheral Protection Control
0x298
read-write
n
0x0
0x0
APBNSPPC[0]
Non-Secure Access APB slave Peripheral Protection Control
0xE0
read-write
n
0x0
0x0
APBNSPPC[1]
Non-Secure Access APB slave Peripheral Protection Control
0x154
read-write
n
0x0
0x0
APBNSPPC[2]
Non-Secure Access APB slave Peripheral Protection Control
0x1CC
read-write
n
0x0
0x0
APBNSPPC[3]
Non-Secure Access APB slave Peripheral Protection Control
0x248
read-write
n
0x0
0x0
APBSPPPC0
Secure Unprivileged Access APB slave Peripheral Protection Control
0xB0
-1
read-write
n
0x0
0x0
APBSPPPC1
Secure Unprivileged Access APB slave Peripheral Protection Control
0xB4
-1
read-write
n
0x0
0x0
APBSPPPC2
Secure Unprivileged Access APB slave Peripheral Protection Control
0xB8
-1
read-write
n
0x0
0x0
APBSPPPC3
Secure Unprivileged Access APB slave Peripheral Protection Control
0xBC
-1
read-write
n
0x0
0x0
APBSPPPCEXP0
Expansion Secure Unprivileged Access APB slave Peripheral Protection Control
0xC0
-1
read-write
n
0x0
0x0
APBSPPPCEXP1
Expansion Secure Unprivileged Access APB slave Peripheral Protection Control
0xC4
-1
read-write
n
0x0
0x0
APBSPPPCEXP2
Expansion Secure Unprivileged Access APB slave Peripheral Protection Control
0xC8
-1
read-write
n
0x0
0x0
APBSPPPCEXP3
Expansion Secure Unprivileged Access APB slave Peripheral Protection Control
0xCC
-1
read-write
n
0x0
0x0
APBSPPPCEXP[0]
Expansion Secure Unprivileged Access APB slave Peripheral Protection Control
0x180
read-write
n
0x0
0x0
APBSPPPCEXP[1]
Expansion Secure Unprivileged Access APB slave Peripheral Protection Control
0x244
read-write
n
0x0
0x0
APBSPPPCEXP[2]
Expansion Secure Unprivileged Access APB slave Peripheral Protection Control
0x30C
read-write
n
0x0
0x0
APBSPPPCEXP[3]
Expansion Secure Unprivileged Access APB slave Peripheral Protection Control
0x3D8
read-write
n
0x0
0x0
APBSPPPC[0]
Secure Unprivileged Access APB slave Peripheral Protection Control
0x160
read-write
n
0x0
0x0
APBSPPPC[1]
Secure Unprivileged Access APB slave Peripheral Protection Control
0x214
read-write
n
0x0
0x0
APBSPPPC[2]
Secure Unprivileged Access APB slave Peripheral Protection Control
0x2CC
read-write
n
0x0
0x0
APBSPPPC[3]
Secure Unprivileged Access APB slave Peripheral Protection Control
0x388
read-write
n
0x0
0x0
BRGINTCLR
Bridge Buffer Error Interrupt Clear
0x44
write-only
n
0x0
0x0
BRGINTEN
Bridge Buffer Error Interrupt Enable
0x48
read-write
n
0x0
0x0
BRGINTSTAT
Bridge Buffer Error Interrupt Status
0x40
read-only
n
0x0
0x0
NSCCFG
Non Secure Callable Configuration for IDAU
0x14
read-write
n
0x0
0x0
NSMSCEXP
Expansion MSC Non-Secure Configuration
0xD0
read-only
n
0x0
0x0
SECMPCINTSTATUS
Secure MPC Interrupt Status
0x1C
read-only
n
0x0
0x0
SECMSCINTCLR
Secure MSC Interrupt Clear
0x34
write-only
n
0x0
0x0
SECMSCINTEN
Secure MSC Interrupt Enable
0x38
read-write
n
0x0
0x0
SECMSCINTSTAT
Secure MSC Interrupt Status
0x30
read-only
n
0x0
0x0
SECPPCINTCLR
Secure PPC Interrupt Clear
0x24
write-only
n
0x0
0x0
SECPPCINTEN
Secure PPC Interrupt Enable
0x28
read-write
n
0x0
0x0
SECPPCINTSTAT
Secure PPC Interrupt Status
0x20
read-only
n
0x0
0x0
SECRESPCFG
Security Violation Response Configuration Register
0x10
read-write
n
0x0
0x0
SSP0
SPI 0 (Non-Secure)
SPI
0x0
0x0
0x40
registers
n
SPI0
SPI 0 interrupt
51
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SSP0_Secure
SPI 0 (Secure)
SPI
0x0
0x0
0x40
registers
n
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SSP1
SPI 1 (Non-Secure)
SPI
0x0
0x0
0x40
registers
n
SPI1
SPI 1 interrupt
52
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SSP1_Secure
SPI 1 (Secure)
SPI
0x0
0x0
0x40
registers
n
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SSP2
SPI 2 (Non-Secure)
SPI
0x0
0x0
0x40
registers
n
SPI2
SPI 2 interrupt
53
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SSP2_Secure
SPI 2 (Secure)
SPI
0x0
0x0
0x40
registers
n
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SSP3
SPI 3 (Non-Secure)
SPI
0x0
0x0
0x40
registers
n
SPI3
SPI 3 interrupt
54
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SSP3_Secure
SPI 3 (Secure)
SPI
0x0
0x0
0x40
registers
n
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SSP4
SPI 4 (Non-Secure)
SPI
0x0
0x0
0x40
registers
n
SPI4
SPI 4 interrupt
55
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
SSP4_Secure
SPI 4 (Secure)
SPI
0x0
0x0
0x40
registers
n
CPSR
Clock prescale register
0x10
read-write
n
0x0
0x0
CPSDVSR
Clock prescale divisor
0
8
CR0
Control register 0
0x0
read-write
n
0x0
0x0
DSS
Data Size Select
0
4
FRF
Frame format
4
6
SCR
Serial clock rate
8
16
SPH
SSPCLKOUT phase
7
8
SPO
SSPCLKOUT polarity
6
7
CR1
Control register 1
0x4
read-write
n
0x0
0x0
LBM
Loop back mode
0
1
MS
Master or slave mode select
2
3
SOD
Slave-mode output disable
3
4
SSE
Synchronous serial port enable
1
2
DMACR
DMA control register
0x24
read-write
n
0x0
0x0
RXDMAE
Receive DMA Enable
0
1
TXDMAE
Transmit DMA Enable
1
2
DR
Data register
0x8
read-write
n
0x0
0x0
Data
Transmit/Receive FIFO
0
16
ICR
Interrupt clear register
0x20
write-only
n
0x0
0x0
RORIC
Clears the SSPRORINTR interrupt
0
1
RTIC
Clears the SSPRTINTR interrupt
1
2
IMSC
Interrupt mask set or clear register
0x14
read-write
n
0x0
0x0
RORIM
Receive overrun interrupt mask
0
1
RTIM
Receive timeout interrupt mask
1
2
RXIM
Receive FIFO interrupt mask
2
3
TXIM
Transmit FIFO interrupt mask
3
4
MIS
Masked interrupt status register
0x1C
read-only
n
0x0
0x0
RORMIS
receive over run masked interrupt state
0
1
RTMIS
receive timeout masked interrupt state
1
2
RXMIS
receive FIFO masked interrupt state
2
3
TXMIS
transmit FIFO masked interrupt state
3
4
RIS
Raw interrupt status register
0x18
read-only
n
0x0
0x0
RORRIS
receive over run raw interrupt state
0
1
RTRIS
receive timeout raw interrupt state
1
2
RXRIS
receive FIFO raw interrupt state
2
3
TXRIS
transmit FIFOraw interrupt state
3
4
SR
Status register
0xC
read-only
n
0x0
0x0
BSY
PrimeCell SSP busy flag
4
5
RFF
Receive FIFO full
3
4
RNE
Receive FIFO not empty
2
3
TFE
Transmit FIFO empty
0
1
TNF
Transmit FIFO not full
1
2
TIMER0
Timer 0 (Non-Secure)
Timer
0x0
0x0
0x10
registers
n
TIMER0
Timer 0 interrupt
3
CTRL
Control Register
0x0
read-write
n
0x0
0x0
ENABLE
Enable
0
1
Disable
Timer is disabled
0
Enable
Timer is enabled
1
EXTCLK
External Clock Enable
2
3
Disable
External Clock s disabled
0
Enable
External Clock is enabled
1
EXTIN
External Input as Enable
1
2
Disable
External Input as Enable is disabled
0
Enable
External Input as Enable is enabled
1
INTEN
Interrupt Enable
3
4
Disable
Interrupt is disabled
0
Enable
Interrupt is enabled
1
INTCLEAR
Timer Interrupt clear register
INTSTATUS
0xC
write-only
n
0x0
0x0
oneToClear
INTSTATUS
Timer Interrupt status register
0xC
read-only
n
0x0
0x0
RELOAD
Counter Reload Value
0x8
read-write
n
0x0
0x0
VALUE
Current Timer Counter Value
0x4
read-write
n
0x0
0x0
TIMER0_Secure
Timer 0 (Secure)
Timer
0x0
0x0
0x10
registers
n
CTRL
Control Register
0x0
read-write
n
0x0
0x0
ENABLE
Enable
0
1
Disable
Timer is disabled
0
Enable
Timer is enabled
1
EXTCLK
External Clock Enable
2
3
Disable
External Clock s disabled
0
Enable
External Clock is enabled
1
EXTIN
External Input as Enable
1
2
Disable
External Input as Enable is disabled
0
Enable
External Input as Enable is enabled
1
INTEN
Interrupt Enable
3
4
Disable
Interrupt is disabled
0
Enable
Interrupt is enabled
1
INTCLEAR
Timer Interrupt clear register
INTSTATUS
0xC
write-only
n
0x0
0x0
oneToClear
INTSTATUS
Timer Interrupt status register
0xC
read-only
n
0x0
0x0
RELOAD
Counter Reload Value
0x8
read-write
n
0x0
0x0
VALUE
Current Timer Counter Value
0x4
read-write
n
0x0
0x0
TIMER1
Timer 1 (Non-Secure)
Timer
0x0
0x0
0x10
registers
n
TIMER1
Timer 1 interrupt
4
CTRL
Control Register
0x0
read-write
n
0x0
0x0
ENABLE
Enable
0
1
Disable
Timer is disabled
0
Enable
Timer is enabled
1
EXTCLK
External Clock Enable
2
3
Disable
External Clock s disabled
0
Enable
External Clock is enabled
1
EXTIN
External Input as Enable
1
2
Disable
External Input as Enable is disabled
0
Enable
External Input as Enable is enabled
1
INTEN
Interrupt Enable
3
4
Disable
Interrupt is disabled
0
Enable
Interrupt is enabled
1
INTCLEAR
Timer Interrupt clear register
INTSTATUS
0xC
write-only
n
0x0
0x0
oneToClear
INTSTATUS
Timer Interrupt status register
0xC
read-only
n
0x0
0x0
RELOAD
Counter Reload Value
0x8
read-write
n
0x0
0x0
VALUE
Current Timer Counter Value
0x4
read-write
n
0x0
0x0
TIMER1_Secure
Timer 1 (Secure)
Timer
0x0
0x0
0x10
registers
n
CTRL
Control Register
0x0
read-write
n
0x0
0x0
ENABLE
Enable
0
1
Disable
Timer is disabled
0
Enable
Timer is enabled
1
EXTCLK
External Clock Enable
2
3
Disable
External Clock s disabled
0
Enable
External Clock is enabled
1
EXTIN
External Input as Enable
1
2
Disable
External Input as Enable is disabled
0
Enable
External Input as Enable is enabled
1
INTEN
Interrupt Enable
3
4
Disable
Interrupt is disabled
0
Enable
Interrupt is enabled
1
INTCLEAR
Timer Interrupt clear register
INTSTATUS
0xC
write-only
n
0x0
0x0
oneToClear
INTSTATUS
Timer Interrupt status register
0xC
read-only
n
0x0
0x0
RELOAD
Counter Reload Value
0x8
read-write
n
0x0
0x0
VALUE
Current Timer Counter Value
0x4
read-write
n
0x0
0x0
UART0
UART 0 (Non-Secure)
UART
0x0
0x0
0x14
registers
n
UART0_RX
UART 0 RX interrupt
32
UART0_TX
UART 0 TX interrupt
33
UART0
UART 0 combined interrupt
42
UART_OVF
UART 0/1/2/3/4 overflow interrupt
47
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART0_Secure
UART 0 (Secure)
UART
0x0
0x0
0x14
registers
n
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART1
UART 1 (Non-Secure)
UART
0x0
0x0
0x14
registers
n
UART1_RX
UART 1 RX interrupt
34
UART1_TX
UART 1 TX interrupt
35
UART1
UART 1 combined interrupt
43
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART1_Secure
UART 1 (Secure)
UART
0x0
0x0
0x14
registers
n
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART2
UART 2 (Non-Secure)
UART
0x0
0x0
0x14
registers
n
UART2_RX
UART 2 RX interrupt
36
UART2_TX
UART 2 TX interrupt
37
UART2
UART 2 combined interrupt
44
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART2_Secure
UART 2 (Secure)
UART
0x0
0x0
0x14
registers
n
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART3
UART 3 (Non-Secure)
UART
0x0
0x0
0x14
registers
n
UART3_RX
UART 3 RX interrupt
38
UART3_TX
UART 3 TX interrupt
39
UART3
UART 3 combined interrupt
45
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART3_Secure
UART 3 (Secure)
UART
0x0
0x0
0x14
registers
n
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART4
UART 4 (Non-Secure)
UART
0x0
0x0
0x14
registers
n
UART4_RX
UART 4 RX interrupt
40
UART4_TX
UART 4 TX interrupt
41
UART4
UART 4 combined interrupt
46
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
UART4_Secure
UART 4 (Secure)
UART
0x0
0x0
0x14
registers
n
BAUDDIV
Baudrate Divider
0x10
read-write
n
0x0
0x0
CTRL
UART Control Register
0x8
read-write
n
0x0
0x0
HSTX
High Speed Test Mode for TX only
6
7
Disable
Disabled
0
Enable
Enabled
1
RVOVINT
RX Overrun Interrupt Enable
5
6
Disable
Disabled
0
Enable
Enabled
1
RXEN
RX Enable
1
2
Disable
Disabled
0
Enable
Enabled
1
RXINT
RX Interrupt Enable
3
4
Disable
Disabled
0
Enable
Enabled
1
TXEN
TX Enable
0
1
Disable
Disabled
0
Enable
Enabled
1
TXINT
TX Interrupt Enable
2
3
Disable
Disabled
0
Enable
Enabled
1
TXOVINT
TX Overrun Interrupt Enable
4
5
Disable
Disabled
0
Enable
Enabled
1
DATA
Recieve and Transmit Data Value
0x0
read-write
n
0x0
0x0
INTCLEAR
UART Interrupt CLEAR Register
INTSTATUS
0xC
write-only
n
0x0
0x0
RXINT
RX interrupt
1
2
oneToClear
RXOV
RX Overrun interrupt
3
4
oneToClear
TXINT
TX interrupt
0
1
oneToClear
TXOV
TX Overrun interrupt
2
3
oneToClear
INTSTATUS
UART Interrupt Status Register
0xC
read-only
n
0x0
0x0
RXINT
RX interrupt
1
2
RXOV
RX Overrun interrupt
3
4
TXINT
TX interrupt
0
1
TXOV
TX Overrun interrupt
2
3
STATE
UART Status Register
0x4
read-write
n
0x0
0x0
RXBF
RX Buffer Full
1
2
read-only
RXOV
RX Buffer Overun (write 1 to clear)
3
4
oneToClear
TXBF
TX Buffer Full
0
1
read-only
TXOV
TX Buffer Overun (write 1 to clear)
2
3
oneToClear
WATCHDOG
Watchdog Timer
WATCHDOG
0x0
0x0
0xC04
registers
n
WATCHDOG
Watchdog interrupt
0
CONTROL
Control Register
0x8
read-write
n
0x0
0x0
INTEN
Interrupt event enable
0
1
Disable
Disable Watchdog interrupt
0
Enable
Enable Watchdog interrupt
1
RESEN
Watchdog reset output enable
1
2
Disable
Disable Watchdog reset
0
Enable
ENable Watchdog reset
1
INTCLR
Interrupt Clear Register
0xC
write-only
n
0x0
0x0
INT
Interrupt
0
1
oneToClear
LOAD
Load Register
0x0
read-write
n
0x0
0x0
LOCK
Lock Register
0xC00
read-write
n
0x0
0x0
MIS
Mask Interrupt Status Register
0x14
read-only
n
0x0
0x0
MIS
Masked Watchdog interrupt
0
1
RIS
Raw Interrupt Status Register
0x10
read-only
n
0x0
0x0
RIS
Raw watchdog interrupt
0
1
VALUE
Value Register
0x4
read-only
n
0x0
0x0